Self-aligned gate MESFET and the method of fabricating same

ABSTRACT

An improved performance MESFET device incorporating a structure fabricated utilized self-aligned gate process technology. The edges of the gate electrode formed are separated from the edges of the dopant regions implanted in the device substrate by a distance which optimizes device performance. In order to increase process yield, a layer of dielectric material is deposited on the substrate surface and then annealed to protect the gate electrode and both stabilize and planarize the substrate surface.

The Government has rights in this invention pursuant to Contract No.F33615-81-C-1427 awarded by the Department of the Air Force.

This application is a continuation of application Ser. No. 505,148,filed June 17, 1983.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to an improved method for fabricating metalsemiconductor field effect transistor (MESFET) devices, and, inparticular, a method for fabricating a self-aligned gate MESFET whereinthe separation between the gate electrode and the dopant self-alignedcontact is controlled to optimize the parasitic source resistance togate capacitance ratio thus improving device performance.

2. Description of the Prior Art

Factors which have limited the performance and yields obtainable inconventional FET processing techniques are the need to perform either(1) a precise recess etch to reduce the FET pinch-off voltage, or (2) acritical realignment of the gate electrode to an existing active channelregion to reduce source resistance. A prior art technique solution tothese problems is disclosed in the articles "A Self-Aligned Source/DrainPlanar Device for Ultrahigh-Speed GaAs MESFET VLSIs" by N. Yokoyama, etal., ISSCC Digest of Technical Papers, pp. 218-219 (February 1981), and"Ti/W Silicide Gate Technology for Self-Aligned GaAs MESFET VLSI's" byYokoyama, et al., International Electron Device Meeting Proceeding, pp.80 (1981). In particular, a fabrication process is described wherein anactive channel layer is formed on a semi-insulating substrate and arefractory metal gate is used as a self-aligned mask for an implantwhich established the n⁺ contact regions. In this instance, the MESFETPinch off voltage is controlled by the channel implant (no recess etchis required) and the source parasitic resistance is reduced by theself-aligned n⁺ contact implant.

A critical factor in using self-aligned gate techniques is the proximityof the n⁺ regions to the gate. A tradeoff exists between parasiticsource-gate resistance and parasitic gate capacitance as the proximityof the n⁺ contact close to the gate lowers the parasitic resistance (asdiscussed in Yokoyama et al. articles) but raises the gate capacitanceand vice versa. Further, the position of the n⁺ regions with respect tothe gate also influences the breakdown voltage of the gate contact tosemiconductor Schottky barrier.

The process described in the Yokoyama et al. references approaches thetradeoff problem by varying the depth of the buried n⁺ implant relativeto the channel implant. A problem with this approach is the relativelyhigh resistivity layer between the ohmic contact and the peak of the n⁺implant, a problem inherent in the use of a buried implant where acurrent path to the surface must exist. This reduces device switchingspeeds, increases power requirements in digital circuits and increasesthe noise factor while lowering the frequency response when the deviceis utilized in analog circuits.

SUMMARY OF THE INVENTION

The present invention provides an improved selfaligned gate process forfabricating metal semiconductor field effect transistors MESFETS andintegrated circuits In particular, an active channel layer is formed ona semi-insulating semiconductor substrate, preferably GaAs, and arefractory metal layer is deposited on the substrate surface. The gateelectrode is fabricated by forming a mask of a predetermined width overthe metal layer, the mask comprising a selectively non-etchablematerial. An undercut etch method is utilized to make the final gatewidth smaller than the width of the gate mask, the gate mask thereafterbeing utilized as the mask for the implantation of the dopant into thesubstrate. The gate mask is then removed and a dielectric layer isdeposited over the surface of the substrate and then annealed, thusprotecting and planarizing the substrate surface and increasing processyields. Ohmic contacts are formed by etching openings in the insulatinglayer to allow contact to the n⁺ implant and device fabrication iscompleted by both the deposit of a second dielectric layer over theprotection dielectric layer and the formation of a metal on the seconddielectric layer.

The MESFET devices produced by the process of the present inventionprovides many advantages over the prior art. The gate formed by theundercut etch allows the spacing between the self-aligned contact andthe gate electrode to be selected such that the ratio of parasiticresistance to gate capacitance is optimized thus increasing switchingspeeds, increasing breakdown voltages and lowering device powerconsumption in digital circuits while also lowering noise and increasingfrequency response when the device is utilized in analog circuits. Theresultant physical gate electrode is shorter than those produced bystandard liftoff methods thus allowing the size (and capacitance) of thedevice to be correspondingly reduced. The deposition of the dielectriclayer on the substrate surface and the annealing thereof after thedopant implant increases process yields, thus reducing manufacturingcosts, by protecting the gate metal electrode and the substrate surfacefrom damage, while also stabilizing the semiconductor surface. Thedielectric layer, in addition, planarizes the substrate surface so thatsubsequent process steps can be accomplished on substantially flatsurfaces, increasing the accuracy, repeatability and yields of MESFETfabrication.

The MESFET devices produced by the fabrication process of the presentinvention have the necessary operating characteristics to be used in themanufacture of high speed digital circuits and in the manufacture oflower noise, higher frequency analog type devices used, such circuitsand devices being used, for example, in computer, communication, missileand radar systems.

BRIEF DESCRIPTION OF THE DRAWING

For a better understanding of the invention as well as other advantagesand further features thereof, reference is made to the followingdescription which is to be read in conjunction with the accompanyingdrawing wherein the same reference numerals, it should be noted,identify identical components in each of the figures, and wherein:

FIG. 1 is a cross-sectional view of a GaAs MESFET fabricated inaccordance with a prior art self-aligned gate process;

FIG. 2 is a cross-sectional view of one embodiment of a GaAs MESFETfabricated in accordance with the improved self-aligned gate process ofthe present invention; and

FIGS. 3-7 are cross-sectional views which illustrate the method offabricating the MESFET of FIG. 2.

DETAILED DESCRIPTION OF THE INVENTION

It should be noted that although the detailed description that followsis related to a GaAs FET structure, specifically GaAs MESFET structures,it will be understood that the invention is suitable for other III-Vmaterials, such as indium phosphide (I_(n) P), used in similarapplications and that the techniques described can be applied to otherFET structures such as MOSFET structures when insulating layers can beachieved.

In order to put the present invention in perspective, a conventionalprior art GaAs MESFET structure will first be described. FIG. 1 depictssuch a prior art structure, as described in the above-mentioned Yokoyamaarticles, the structure comprising a semiinsulating substrate 10, suchas GaAs, typically having a resistivity of about 10⁷ ohm-cm. Substrate10 has an active layer of material 12 supported thereon, layer 12 beingan active semiconductor region having an N-type dopant. Layer 12provides an active region for conduction and control of carriers.Electrodes 14 and 16 are in direct contact with layer 12 and, in FETdevices, serve as source and drain electrodes, respectively. Gateelectrode 18, having a width W of 1.5 μm, contacts a portion of layer 12and is spaced from electrodes 14 and 16.

During the fabrication process, a titanium/tungsten (Ti/W) or tungstensilicide (W/Si) mixture is deposited by dc sputtering and etching isperformed with a Freon and oxygen (CF₄ O₂) gas plasma. The n⁺ layers 19are made by self-aligned Si⁺ implantation using gate 18 as theimplantation mask. Fabrication is completed by ohmic metalization withAuGe-Au in accordance with standard techniques. The edges 17 of the n⁺regions 19 formed by the above described process are, it is observed,aligned with the edges 21 of gate electrode 18. The disadvantages ofthis alignment feature is that the relative closeness of the edges 21relative to regions 19 reduces device performance due to the parasiticcapacitance factors inherent with device utilization, and decreases thereverse breakdown of the gate.

In accordance with the present invention, an improved self-aligned gateFET structure is provided. A MESFET device 20 incorporating thestructure is shown in FIG. 2. It should be noted that although thedevice shown in FIG. 2 and fabricated in accordance with the steps shownin FIGS. 3-7 describe an enhancement mode (ENFET) type device, otnertype devices, including a depletion mode (DFET) device, can befabricated utilizing the techniques of the present invention.

Device 20 comprises a GaAs substrate 22 having n⁺ source and drainregions 26 and 27. An active channel 24 is formed at the upper surfaceof GaAs substrate 22 and a gate electrode 28 of width W₂ is in contactwith the surface of substrate 22. A silicon nitride layer 29 overliesthe surface of substrate 22 and conductive ohmic metal contacts 30 and32 make contact to source and drain regions 26 and 27, respectively,through holes etched in dielectric layer 29. The edges 23 and 25 of n⁺regions 26 and 27, respectively, it can be seen, are not aligned withthe edges of gate 28. In particular, the width of gate 28 is such thatit is less than the separation between edges 23 and 25 of n⁺ regions 26and 27, respectively. For comparison purposes, the aformentionedseparation between gate 28 and edge 25 is about 0.4 μm, the typicalwidth W₂ of gate electrodes 28 being on the order of 0.85 μm. Theadvantages of having a separation between the gate electrode edges andn+ region edges 23 and 25 have been set forth previously, and will bedescribed in more detail hereinafter. The MESFET 20 is completed bydepositing an interconnection crossover dielectric layer 36, typicallysilicon oxynitride, on layer 29 and then etching holes into dielectriclayer 36 to allow a top metal (typically chromium, platinum and gold) toform a second level of metal interconnect 38.

Referring now to FIG. 3, in order to fabricate MESFET 20 by the presentinvention, one starts with a substrate or body 22 of semi-insulatingGaAs. It is noted that other materials can be used for substrate 22,including other III∝V materials, such as InP, and mixed III-Vsemiconductor material such as undoped Al_(x) Ga_(1-x) As (galliumaluminum arsenide). An active layer or channel 24 is formed on thesurface of substrate 22 by introducing a layer of n type dopants by ionimplantation techniques. In the preferred embodiment, silicon ions areimplanted at an energy of about 100 KeV to a dosage in the range fromabout 1×10¹² ions/cm² to about 4×10¹² ions/cm². The thickness of theactive layer typically is in the range from about 500 Å to about 2000 Å.Other processes which can be used to form the active channel 24 includeliquid phase epitaxy, vapor phase epitaxy metal-organic chemical vapordeposition of and molecular beam epitaxy. Ion implantation techniquesare preferred for the remaining process steps. Other n-type dopantswhich could be utilized to form active channel 24 include, for example,selenium, sulphur or tellerium, implanted at energies and dosages whichdepend on the substrate material and quality and the type of MESFETdevice to be fabricated.

A layer of refractory metal gate material 26 is deposited on the surfaceof substrate 22 by rf or dc sputter deposition techniques. Layer 26,having a thickness in the range from about 1000 Å to about 5000 Å,preferably comprises a titanium/tungsten alloy. Compositions of 30%titanium and 70% tungsten by weight have been sucessfully utilized.Other materials which can be utilized as the gate layer include, forexample, tungsten, tantalum, titaniumtungsten silicide, tungstensilicide, tantalum silicide, or molybdenum silicide.

Referring now to FIG. 4, a photoresist layer 40 is next applied to thesurface of layer 26. The photoresist layer 40 is defined usingconventional photolithography processes and developed to provide a maskwhich exposes area 42 of metal film 26 which, as will be set forthhereinafter, defines the edges of the implanted dopant of the MESFETdevice being fabricated. A layer of etch resistant metal 44, such asnickel or aluminum, is formed over photoresist 40 and area 42 byevaporation deposition techniques. The process is carried out for a timesufficient to grow the layer 44 to a thickness in the range from about1000 Å to about 2000 Å.

Then, the photoresist layer 40 is dissolved using conventionaltechniques, a layer 46 of etch resistant metal having a widthcorresponding to the area 42 remaining as shown in FIG. 5.

Referring now to FIG. 6, the substrate 22 is placed in a plasma reactorwith Freon and oxygen (CF₄ +O₂) in order to etch the unmasked portionsof layer 26. It should be noted that although a plasma etch ispreferred, wet chemical or vapor etching can also be utilized. The etchrate can be controlled in a manner to encourage undercut etching, i.e.,etching beneath the unmasked layer 26. Further, the etching process issuch that the mask layer 46 is slightly undercut symmetrically in stagesat a substantially uniform rate. It has been found that a value of theundercut, S, in the range from about 500 Å to about 2500 Å provides theoptimum performance results for MESFET 20, a value of S in the rangefrom 1000 Å to about 2000 Å having been determined to provide the bestperformance results. After the etching process, the width of gateelectrode 28 for an undercut of 2000 Å (4000 Å total) is approximately0.85 μm.

Mask undercutting can be controlled by ascertaining the etch rate timefor the non-mask area of layer 26 and then using that rate to controlthe undercut rate. This can be accomplished directly by process operatoror automatically.

For the plurality of MESFET's being fabricated on a wafer, only onevalue of S need be selected to optimize the performance for that type ofMESFET although S can have a standard deviation in the range from about400 Å to about 500 Å. If S is selected to be 2000 Å, for example, thedeviation in S from MESFET to MESFET will not be sufficient to reducethe overall performance improvement in each MESFET fabricated.

Then substrate 22 is flood exposed to silicon ions (represented by thearrows 47) in order to form the heavily doped regions (n⁺ in the exampleillustrated) 27' and 27 corresponding to the source and drain regions,respectively. The silicon donor impurities are introduced by ionimplantation of silicon ions at an energy of about 125 KeV to a dosageof about 2×10¹³ ions/cm². The remaining metal layer 46 is then removedby an appropriate chemical selective solvent. Regions 27' and 27 have athickness in the range from about 500 Å to about 3000 Å.

Referring now to FIG. 7, substrate 22 is placed into a plasma enhancedvapor deposition reactor and a silicon nitride (Si₃ N₄) protective layer29 is deposited over the surface of substrate 22. Other known depositionreactions, such as the thermal reaction of silane (SiH₄) and ammonia(NH₃) may be employed. The process is carried out for a time sufficentto form the layer 29 to a thickness in the range from about 1000 Å toabout 2000 Å. The substrate is then annealed at approximately 800° F.for approximately 10 minutes. The annealing step minimizes the damagecaused to the substrate crystal structure after ion implantation (n⁺ inthe example described) at high energy levels. Other dielectrics whichcan be utilized include SiO₂ and Al₂ O₃.

Then, an anisotropic plasma etch, using either C₂ F₆, C₃ F₈ or CHF₃,removes portions of the Si₃ N₄, and forms holes to provide for ohmiccontact definition. The holes are filled with ohmic contact material 30and 32, typically a composition of gold and germanium, to allow forconnection to the underlying source and drain semiconductor regions. Thesubstrate is then heated to 360° F. in order to improve the contactbetween material 30 and 32 and the adjacent n⁺ regions 27. The surface33 of layer 39 is substantially planar except for the relatively small"bump" area adjacent to electrode 28. A hole is etched (not shown) inlayer 29 to enable a metal connect to gate electrode 28.

Although not shown in the figure since it is not part of the MESFETdevice 20 finally fabricated, each device on the wafer is isolated fromthe adjacent device to prevent electron leakage. In particular, aphotoresist layer is deposited on the dielectric layer 20 to mask theconducting regions and boron ions are implanted around the sides of eachdevice at an energy of about 80 KeV to a dosage of about 1×10¹³ions/cm². After the implant, the photoresist mask is chemically removed.

Finally, using conventional procedures, a second dielectric layer 36(FIG. 2) may be deposited over layer 29 to allow for crossoverconnections and metal layer 38, typically chromium, platinum, and gold,is deposited over layer 36, the metal layer 38 being defined and etchedusing conventional photolithographic processes, well known in the art,to complete the device 20 shown in FIG. 2.

EXAMPLE

Devices substantially depicted in FIG. 2 have been fabricated inaccordance with the process steps described hereinabove with referenceto FIGS. 3-7. Typical devices have an active region (n-type) doped withSi to 10¹² ions/cm². The thickness of the active region varied from 500Å to about 2000 Å, the dopant regions varied in thickness from about 500Å to about 3000 Å, the undercut value S for the electrode gate variedfrom about 1000 Å to about 2000 Å, and the silicon nitride protectivelayer varied in thickness from about 1000 Å to about 2000 Å.

The measured electrical properties of two ENFET devices fabricated inaccordance with the teachings of the present invention were as follows(both devices 28 μm wide, threshold voltage 0.2 volts): For a 1.1 μmgate width, the drain-source current I_(DS) =17.8 ma/mm; thetransconductance, gm=90 mS/mm; gate voltage V_(G) =0.6 volts;drain-source voltage V_(DS) =1 volt. For a 0.8 μm gate width, I_(DS)=26.8 ma/mm; gm=140 mS/mm at V_(G) =0.6 volts and V_(DS) =1 volt.

The self-aligned gate process described hereinabove thus providessignificant advantages over prior art MESFET processes by increasingboth device performance and process yields. Performance is significantlyincreased by providing a technique for optimizing the parasitic sourceresistance and parasitic gate capacitance ratio which normally limitsdevice performance. The measure of the speed capability of MESFETs,f_(t), is given by a g_(m) '/2πC_(g) wherein ##EQU1## g_(m) ' and g_(m)being the terminal and intrinsic transconductance respectively, R_(s) isthe parasitic source resistance and C_(g) the total gate capacitance.Optimization is possible because as S is increased from zero, C_(g)decreases more rapidly than R_(s) increases, thus establishing thatthere is an optimum separation S (wider separations produce increasedgate breakdown thus allowing higher gate voltages).

Thus, by controlling the separation between the edges of the dopantimplant and the edges of the gate electrode in accordance with theteachings of the present invention, MESFET performance is enhancedwithout significantly increasing the cost of device fabrication.Comparing the switching speed of devices formed in accordance with theteaching of the present invention to devices performing the samefunction and fabricated with prior art techniques, an ENFETring-oscillator fabricated in accordance with the invention provided a25 psec gate delay (for a gate width 0.85 μm) as compared to the 50 psecdelay of an oscillator fabricated by the prior art process describedhereinabove (gate width 1.1 μm). The power dissipation was alsosignificantly reduced from 6.5 mw/gate (at V_(D) =5 volts) to 3.3mw/gate (at V_(D) =2.6 volts). Additional advantages in utilizing theprocess of the present invention is that the gate electrode width willalways be smaller than the gate mask width, thus enabling device size tobe further reduced from that available in the prior art. The dielectriclayer enables process yields to increase by stabilizing and passivatingthe substrate surface (prevents the arsenic component of the substratefrom escaping during the annealing step following dopant implantationand also protects the substrate surface from exposure to theenvironment); protecting the gate electrode; and planarizing thesubstrate surface to allow subsequent processing steps to be accuratelyaccomplished.

While the invention has been described with reference to its preferredembodiments, it will be understood by those skilled in the art thatvarious changes may be made and equivalents may be substituted forelements thereof without departing from the true nature and scope of theinvention. In addition, many modifications may be made to adapt aparticular situation or material to the teachings of the presentinvention without departing from its essential teachings.

What is claimed is:
 1. A MESFET device comprising:a substrate ofsemi-insulating III-V semiconductor material; a doped active channellayer of III-V semiconductor material containing impurities of aselected conductivity type formed in a surface portion of saidsubstrate; first and second doped regions containing a heavierconcentration of impurities of said selected conductivity type formed insaid substrate at respective locations adjacent opposite ends of saidchannel layer; a gate electrode contacting at least a portion of saidactive channel layer and positioned on said substrate surface betweensaid first and second doped regions, the edges of said gate electrodebeing spaced from the respective edges of said first and second dopedregions by a distance of from about 1000 Å to about 2000 Å, whereby aselected optimal ratio of parasitic source resistance to parasitic gatecapacitance is achieved, a layer of dielectric material formed on thesurface of said substrate and overlying said gate electrode and saidfirst and second doped regions; and first and second ohmic contactsextending through said dielectric layer and electrically contacting saidfirst and second doped regions.
 2. The structure of claim 1 wherein saidsemiconductor substrate is of gallium arsenide.
 3. The structure ofclaim 1 wherein said semiconductor substrate is of indium phosphide. 4.A MESFET device comprising:a substrate of semi-insulating III-Vsemiconductor material; a doped active channel layer of III-Vsemiconductor material containing impurities of a selected conductivitytype formed in a surface portion of said substrate, said active channellayer being on the order of about 500 Å to 2000 Å in thickness; firstand second doped regions containing a heavier concentration ofimpurities of said selected conductivity type formed in said substrateat respective locations adjacent opposite ends of said channel layer; agate electrode contacting a portion of said active channel layer andpositioned on said substance surface between said first and second dopedregions, the edges of said gate electrode being spaced from therespective edges of said first and second doped regions by a distance offrom about 1000 Å to about 2000 Å, whereby a selected optimal ratio ofparasitic source resistance to parasitic gate capacitance is achieved; alayer of dielectric material formed on the surface of said substrate andoverlying said gate electrode and said first and second doped regions,said dielectric layer being in the range from about 1000 Å to about 2000Å in thickness; first and second ohmic contacts extending through saiddielectric layer and electrically contacting said first and second dopedregions.
 5. The structure of claim 4 wherein said semiconductorsubstrate is of gallium arsenide.
 6. The structure of claim 4 whereinsaid semiconductor substrate is of indium phosphide.
 7. A MESFET devicecomprising:a semi-insulating gallium arsenide semiconductor substrate; adoped active channel layer of III-V semiconductor material containingimpurities of a selected conductivity type formed on a surface portionof said substrate, said active channel layer being in the order of about500 Å to 2000 Å in thickness; first and second doped regions containinga heavier concentration of impurities of said selected conductivity typeformed in said substrate at respective locations adjacent opposite endsof said channel layer, said doped regions comprising silicon ions andbeing in the range of from about 500 Å to 3000 Å in thickness; a gateelectrode contacting at least a portion of said active channel layer andpositioned on said substrate surface between said first and second dopedregions, the edges of said gate electrode being spaced from therespective edges of said first and second doped regions by a distance offrom about 1000 Å to about 2000 Å, whereby a selected optimal ratio ofthe parasitic source resistance to parasitic gate capacitance isachieved; a layer of silicon nitrate formed on the surface of saidsubstrate and overlying said gate electrode and said first and seconddoped regions, said silicon nitrate layer being in the range of fromabout 1000 Å to about 2000 Å in thickness; first and second ohmiccontacts extending through said dielectric layer and electricallycontacting said first and second doped regions.
 8. The structure ofclaim 7 wherein the thickness of said gate electrode is in the range offrom about 2000 Å to about 5000 Å.